The present invention is directed to tools for designing integrated circuits and, more particularly, to a tool that analyzes timing slack of an integrated circuit design and partitions the design based on the timing slack.
Modern integrated circuits (ICs) are much too complex to be designed manually; instead, they are designed using electronic design automation (EDA) tools. Typically, design of an IC using EDA tools includes the steps of system specification, architectural design, functional and logic design, circuit design, physical design, and physical verification, among others. During the circuit design flow, register-transfer-level (RTL) abstraction is typically used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of the IC. Designs for individual standard cells and their characteristics are selected from a standard cell library, which may include variants of different cells with different performance characteristics, power requirements and floor area, etc. An RTL description is defined in terms of registers that store signal values, and combinational logic that performs logical operations on the signal values. The RTL description is usually converted to a gate-level cell description (such as a netlist) in the synthesis process, which can then be used in the physical design process.
The physical design process typically starts with floor planning. During floor planning, the relative overall positions of items of the IC design are defined, including input/output (I/O) structures, memories, and data paths, as well as processor cores. The floor plan has a major influence on considerations of chip area and operational speed, including routing resources, and interconnection lengths, for example.
The physical design may be divided into partitions. Logical partitioning may be performed before floor planning, in RTL for example, to differentiate functional blocks based on their functionality and characteristics. Partitioning may also be performed or modified after preliminary floor planning. The partitioning may be soft, in which a soft partition is placed and routed and timing closed in conjunction with the rest of the sea of gates (SoG), or may be hard partitioning, in which blocks have physical boundaries (not necessarily contiguous) and are allocated initial timing budgets. These hard partitions are placed and routed, and their timing closed, independent of the rest of the SoG. This process can be iterative and may require the timing budgets for the hard partitions to be revised, iteratively.
After partitioning, the physical design process continues with placement and routing tools and clock tree synthesis to create a physical layout. Optimization of the physical design is performed at various stages, the subsequent stages then iterating to take account of the changes made. Wire length, module area, and variants of standard cells with greater or lesser performance can be substituted for the initial choices if it is found that the performance of the initial choice was insufficient or excessive. Timing budgets may be modified and, for example, timing slack in one element that has positive slack and is faster than its timing budget may be re-apportioned to another element in the same or a related data path and which has negative timing slack and failed to meet its timing budget.
After all opportunities for optimization of this kind have been exploited, it is often in fact the case that a large proportion of the data paths have excess positive timing slack. It is desirable to find a way of benefiting from the excess timing slack of those data paths.